TUTORIALS
NEUROMORPHIC AUDITORY PROCESSING
TEACHERS
Shih-Chii Liu (UZH|ETH, Switzerland), Enea Ceolini (UZH|ETH, Switzerland)
SUMMARY
This tutorial focusses on advances in audio machine learning algorithms that have led to new applications in smart assistants that are currently ubiquitious in devices such as smartphones, laptops, and cars. While the largest challenge of large vocabulary speech recognition can be addressed by powerful but computationally demanding models running in the cloud, many other less complex tasks can be implemented by models running only on the device and which require limited resources and is executable with low latency. This general idea of computing on the edge (fog level), opens up new challenges for ML research that now has to deal with the necessity of having small models that run fast on limited resource devices. These challenges include domains such as personalization, continual training, domain adaptation and especially privacy related issues. This tutorial will be useful for participants who are interested in learning about the ML audio algorithms suitable for embedded low power systems. They will learn about the important steps in developing, training and deploying ML audio models for various applications and the model constraints. Examples of solutions implemented especially for low resource devices and architecture considerations will be presented.
PARTICIPANT TAKEAWAY
- Understand the machine learning audio algorithms suitable for embedded low power systems
- Understand the important steps in developing, training and deploying ML audio models
- Understand the model architecture choices based on the IoT platform constraints
DEMYSTIFYING NEURAL NETWORKS AT THE VERY EDGE OF THE IOT
TEACHERS
Michele Magno (ETH Zurich, Switzerland), Francesco Conti (ETH Zurich & University of Bologna), Manuele Rusci (University of Bologna & GreenWaves Technologies)
SUMMARY
Execution of “heavy” algorithms such as neural networks on platforms with 10-100 mW of power envelope and less than 1 MB of on-chip memory poses two symmetric problems: 1) minimization of memory and computational footprint; 2) maximization of performance and energy efficiency. In this tutorial, we will cover in detail the constraints machine learning algorithms must be subjected to for implementation on low-power end-nodes, as well as several current and future techniques to target these constraints. We range from DNN model distillation/quantization with low-bitwidth integers to the design of AI-dedicated programmable architectures flexible and efficient at the same time, achieving billions of operations per second in a microcontroller power budget. We showcase these concepts on commercial ARM-based Cortex-M class IoT endnodes as well as on RISC-V based parallel ultra-low-power (PULP) processors such as GreenWaves GAP8.
PARTICIPANT TAKEAWAY
- Discover what are the challenges to drive AI to the very edge of the IoT
- Understand the combined architectural and algorithmic techniques to overcome these challenges
- See how these techniques can be applied to commercial low-power IoT endnodes (ARM Cortex-M class, GreenWaves GAP8)
Sponsors
