The limits of embedded AI
An experienced industrial panel will explore the limits of embedded AI. The session will begin with a short introduction from each panel member where they will outline their predictions for the next 5-10 years and what they see as major challenges and research priorities.
The audience will then have the opportunity to ask the panel questions. This will be an exciting opportunity to learn about industry's vision of AI and AI hardware.
Edith Beigné - Facebook
Partha Maji - Arm
Grant Martin - Cadence
Yu Meng - Huawei
Michael Pfeiffer - Bosch
Abu Sebastian - IBM Research
Robert Mullins - University of Cambridge
Edith Beigné joined Facebook Inc. in Menlo Park in November 2018 to lead the AR/VR Silicon Research team. Before that, she was with CEA-LETI, Grenoble, France, from 1998 to 2018 where she was the Research Director of Integrated Circuits and System Division. Since 2009, she has been a senior scientist in the digital and mixed-signal design lab where she focused on low power and adaptive circuit techniques, exploiting asynchronous design and advanced technology nodes like FDSOI 28nm and 14nm for many different applications from high-performance MPSoC to ultra-low power IoT applications. Her main research interests today are low power digital and mixed-signal circuits and design with emerging technologies. She is part of ISSCC TPC since 2014 and part of VLSI’s symposium since 2015. Distinguished Lecturer for the SSCS in 2016/2017, Women-in-Circuits Committee chair and JSSC Associate Editor since 2018. She visited Stanford University in 2018.
Partha Maji is a Principal Research Scientist at Arm's Machine Learning Research Lab based in Cambridge, where he leads the core research on the efficient implementation of probabilistic machine learning on resource-constrained devices. He received a PhD in computer science from the University of Cambridge, where he focussed on optimisation and acceleration of deep neural networks. Prior to that, he received an MSc in system-on-chip design from the University of Edinburgh. Partha spent a decade in the semiconductor industry as a CPU subsystem architect and an ASIC design engineer. He has extensive experience with the end-to-end chip design process through multiple tape-outs of low-power chips at 65/40/28/22nm deep-submicron CMOS process technology. His current research interests lie in multiple disciplines that bridge the topics of machine learning, mobile/embedded systems, computer architecture and hardware implementation. Partha has received several excellence awards from the industry including a Mentor Graphics prize for outstanding achievement in the master’s degree. Partha also received multiple accolades for his research on on-chip interconnect including an award from Epson Europe and the IET, UK. He was also recognized by the European Neural Network Society for high-quality contribution in machine learning research. Partha was a recipient of the prestigious UK Chevening scholarship.
Grant Martin has been a Distinguished Engineer at Cadence, San Jose for 7 years.
Before that he was a Chief Scientist for Tensilica. in Santa Clara, California for 9 years,
prior to its acquisition by Cadence in April 2013.
Earlier in his career, Grant worked for Burroughs in Scotland for 6 years; Nortel/BNR in Canada for 10 years;
and Cadence Design Systems for 9 years (first round), eventually becoming a Cadence Fellow in their Labs.
He received his Bachelor's and Master's degrees in Mathematics (Combinatorics and Optimisation)
from the University of Waterloo, Canada, in 1977 and 1978.
Mr. Yu Meng, who joined Huawei since 18 years ago has been working on the advanced computing architecture, technology strategy as well as business development. He has variety experience of the computing platform based on x86, ARM and heterogeneous acceleration hardware of Huawei product from the edge, network and data center solution. He was once one of the technical leaders of the standardization team of CCIX consortium when Huawei was one of the founders between 2015 and 2016. After being relocated to Germany in Europe in 2016, he has been working on the technical strategy and business development on behalf of Huawei European Research Institute. His latest interest relates to the novel hardware and chip architecture research of machine learning, especially regarding the artificial neural network.
Michael Pfeiffer joined Bosch Corporate Research in November 2016. Until October 2016 he was a group leader at the Institute of Neuroinformatics and program coordinator for the joint MSc program in Neural Systems and Computation by the University of Zurich and ETH Zurich. He did his PhD with Wolfgang Maass at the Institute of Theoretical Computer Science, Graz University of Technology, Austria. Before that he did his undergraduate studies in Technical Mathematics at Graz University of Technology. His research interests are in computational neuroscience, machine learning, and computer vision. He works on algorithmic approaches for understanding computation and learning in the brain, and investigates how such algorithms can be linked to mathematical formalisms such as probabilistic inference, deep learning, and other successful methods used in machine learning. Another main focus of his work is to develop efficient event-based algorithms based on these principles that are suitable for real-world applications of neuromorphic engineering. In particular, he develops algorithms for event-based vision applications that work with sensory input from Silicon Retina sensors such as the Dynamic Vision Sensor (DVS). His focus is on gesture and movement recognition, tracking, object recognition, and sensory fusion.
Abu Sebastian was born in Kerala, India. He received a B. E. (Hons.) degree in Electrical and Electronics Engineering from BITS Pilani, India and M.S. and Ph.D. degrees in Electrical Engineering (minor in Mathematics) from Iowa State University. Since 2006, he is a Research Staff Member at IBM Research - Zurich in Rüschlikon, Switzerland. He was a contributor to several key projects in the space of storage and memory technologies and currently manages the research effort on in-memory computing at IBM Research - Zurich. He has published over 180 articles in journals and conference proceedings. He also holds over 50 granted patents.
Dr. Sebastian is a co-recipient of the 2009 IEEE Control Systems Technology Award and the 2009 IEEE Transactions on Control Systems Technology Outstanding Paper Award. In 2013 he received the IFAC Mechatronic Systems Young Researcher Award for his contributions to the field of mico-/nanoscale mechatronic systems. In 2015 he was awarded the European Research Council (ERC) consolidator grant. He is an IBM Master Inventor since 2016. He was named Principal and Distinguished Research Staff Member in 2018 and 2020, respectively. In 2019 he received the Ovshinsky Lectureship Award for his contributions to "Phase-change materials for cognitive computing".